3D Stacking Paves Way for Smaller, Power-Packed Computing Chips

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Scientists from the Institute of Microelectronics (IME) at the Agency for Science, Technology and Research (A*STAR) have developed breakthrough technology that can stack up to four layers of wafers, potentially decreasing the cost of production by 50 per cent. Defying Limitations to Moore’s Law Computing performance is struggling to keep up with the relentless drive for higher-performing chips, as performance bottlenecks have emerged with scaling reaching the limit on all fronts. One way to extend Moore’s Law is through heterogeneous integration, which can pave the way to future devices with increasing performance levels. As chips become smaller and more powerful, the wires connecting the growing number of transistors get thinner and more densely packed. The resulting increased resistance and overheating can cause signal delays and limit the central processing units (CPU) clock speed. Other issues include frequency limitations in large-scale integrated circuit (LSI) operations, battery-related power limitations, and cooling problems.

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